cystech electronics corp. spec. no. : c698c3 issued date : 2012.07.06 revised date : 2012.10.05 page no. : 1/ 8 MTP1013C3 cystek product specification -20v p-channel enhancement mode mosfet MTP1013C3 bv dss -20v i d -500ma r dson @v gs =-4.5v, i d =-500ma 0.63(typ) r dson @v gs =-2.5v, i d =-300ma 1.1 (typ) r dson @v gs =-1.8v, i d =-150ma 1.7 (typ) features ? very low level gate drive requirements allowing direct operation in 3v circuits. v gs(th) <1.2v. ? compact industrial standard sot-523 surface mount package. ? pb-free package. equivalent circuit outline absolute maximum ratings (tj=25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds -20 gate-source voltage v gs 8 v continuous drain current @ t a =25 c, v gs =-4.5v -0.5 continuous drain current @ t a =70 c, v gs =-4.5v i d -0.4 pulsed drain current *1 i dm -2 a maximum power dissipation @ t a =25 p d 280 *2 mw thermal resistance, junction-to-ambient r th,ja 450 *2 c/w operating junction and storage temperature tj, tstg -55~+150 c note : 1. pulse width 10 s, duty cycle 2%. 2. when mounted on fr-4 board with 1 sq inch pad size. MTP1013C3 sot-523 d g gate s g s source d drain
cystech electronics corp. spec. no. : c698c3 issued date : 2012.07.06 revised date : 2012.10.05 page no. : 2/ 8 MTP1013C3 cystek product specification electrical characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -20 - - v v gs =0v, i d =-250 a v gs(th) -0.5 -0.8 -1.2 v v ds =v gs , i d =-250 a g fs - 0.7 - s v ds =-10v, i d =-250ma i gss - - 2 v gs = 8v, v ds =0 - - -1 v ds =-20v, v gs =0 i dss - - -10 a v ds =-20v, v gs =0, tj=55 c - 0.63 0.9 v gs =-4.5v, i d =-500ma - 1.1 1.4 v gs =-2.5v, i d =-300ma *r ds(on) - 1.7 2.7 v gs =-1.8v, i d =-150ma dynamic ciss - 59 - coss - 21 - crss - 15 - pf v ds =-10v, v gs =0, f=1mhz *t d(on) - 5 - *t r - 6 - *t d(off) - 42 - *t f - 14 - ns v ds =-10v, i d =-200ma, v gs =-4.5v, r g =10 *qg - 1.5 - *qgs - 0.28 - *qgd - 0.44 - nc v ds =-10v, i d =-250ma, v gs =-4.5v source-drain diode *i s - - -0.5 *i sm - - -2 a *v sd - -0.88 -1.2 v v gs =0v, i s =-150ma *pulse test : pulse width 300 s, duty cycle 2% ordering information device package shipping marking MTP1013C3 sot-523 (pb-free package) 3000 pcs / tape & reel tw
cystech electronics corp. spec. no. : c698c3 issued date : 2012.07.06 revised date : 2012.10.05 page no. : 3/ 8 MTP1013C3 cystek product specification typical characteristics typical output characteristics 0 0.4 0.8 1.2 1.6 2 012345678910 -v ds , drain-source voltage(v) -i d , drain current (a) -v gs =1.8v -v gs =2v -v gs =1.5v -v gs =2.5v -v gs =3v -v gs =3.5v -v gs =5v, 4.5v,4v brekdown voltage vs ambient temperature 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) -bv dss , normalized drain-source breakdown voltage i d =-250 a, v gs =0v static drain-source on-state resistance vs drain current 0 2 4 6 8 10 12 0.001 0.01 0.1 1 -i d , drain current(a) r ds(on) , static drain-source on-state resistance() -v gs =2.5v -v gs =1.5v -v gs =1.2v -v gs =1.8v -v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 0.3 0.6 0.9 1.2 1.5 -i dr , reverse drain current (a) -v sd , source-drain voltage(v) tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 024681 0 drain-source on-state resistance vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds( on) , normalized static drain- source on-state resistance v gs =-4.5v, i d =-500ma v gs =-2.5v, i d =-300ma -v gs , gate-source voltage(v) r ds( on) , static drain-source on- state resistance() i d =-500ma i d =-300ma i d =-150ma
cystech electronics corp. spec. no. : c698c3 issued date : 2012.07.06 revised date : 2012.10.05 page no. : 4/ 8 MTP1013C3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 1 10 100 0.1 1 10 100 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 -60 -40 -20 0 20 40 60 80 100 120 140 160 tj, junction temperature(c) -v gs( th) , normalized threshold voltage i d =-250 a single pulse power rating, junction to ambient 0 2 4 6 8 10 0.001 0.01 0.1 1 10 100 pulse width(s) power (w) t j( max) =150c t a =25c r ja =450c/w gate charge characteristics 0 1 2 3 4 5 00.40.81.21.62 qg, total gate charge(nc) -v gs , gate-source voltage(v) i d =-250ma v ds =-10v maximum safe operating area 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 -v ds , drain-source voltage(v) -i d , drain current (a) dc 10ms 100ms 1m 100 s t a =25c, tj=150c, v gs =-4.5v, r ja =450c/w single pulse maximum drain current vs junctiontemperature 0 0.1 0.2 0.3 0.4 0.5 0.6 25 50 75 100 125 150 175 tj, junction temperature(c) -i d , maximum drain current(a) t a =25c, v gs =-4.5v, r ja =450c/w
cystech electronics corp. spec. no. : c698c3 issued date : 2012.07.06 revised date : 2012.10.05 page no. : 5/ 8 MTP1013C3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 200 400 600 800 1000 1200 0 0.5 1 1.5 2 2.5 3 -v gs , gate-source voltage(v) -i d , drain current (ma) -v ds =5v 150c t j = -40c, 0c, 25c power derating curve 0 0.05 0.1 0.15 0.2 0.25 0.3 0 20 40 60 80 100 120 140 160 t a , ambient temperature() p d , power dissipation(w) transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) normalized transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *z ja (t) 4.r ja =450 c/w
cystech electronics corp. spec. no. : c698c3 issued date : 2012.07.06 revised date : 2012.10.05 page no. : 6/ 8 MTP1013C3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c698c3 issued date : 2012.07.06 revised date : 2012.10.05 page no. : 7/ 8 MTP1013C3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. issued date : 2012.07.06 revised date : 2012.10.05 page no. : 8/ 8 spec. no. : c698c3 MTP1013C3 cystek product specification sot-523 dimension *: typical inches marking: millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.0079 0.0157 0.20 0.40 i *0.0197 - *0.50 - b 0.0591 0.0669 1.50 1.70 j 0.0610 0.0650 1.55 1.65 c 0.0118 0.0197 0.30 0.50 k 0.0276 0.0315 0.70 0.80 d 0.0295 0.0335 0.75 0.85 l 0.0224 0.0248 0.57 0.63 e 0.0118 0.0197 0.30 0.50 m 0.0020 0.0059 0.05 0.15 f 0.0039 0.0118 0.10 0.30 n 0.0039 0.0118 0.10 0.30 g 0.0039 0.0118 0.10 0.30 o 0 0.0031 0 0.08 h *0.0197 - *0.50 - notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . n h f 12 3 j a b c d tw g i e style: pin 1.gate 2.source 3.drain 3-lead sot-523 plastic surface mounted package cystek package code: c3 k l o m
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